1. Field of the Invention
The present invention relates to a semiconductor device utilizing a semiconductor thin film having a crystal structure and a fabrication method thereof. Particularly, the present invention relates to a semiconductor device using a thin film transistor (hereinafter, abbreviated as TFT) having an inverted stagger structure.
Further, xe2x80x9csemiconductor devicexe2x80x9d in the specification designates all of devices operated by utilizing semiconductor properties. Accordingly, all of TFTs, AMLCDs (Active Matrix Type Liquid Crystal Display Device) and electronic devices described in the specification are included in the category of semiconductor devices.
2. Description of Related Art
Conventionally, there has been utilized TFT as a switching element of an active matrix type liquid crystal display device (hereinafter, abbreviated as AMLCD). Currently, a product constituting a circuit by TFT utilizing an amorphous silicon film as an active layer is predominant in the market. As structure of TFT, an inverted stagger structure the fabrication steps of which are simple has been adopted frequently.
However, high function formation of AMLCD has been progressed year by year and operational function (particularly, operational speed) requested to TFT tends to become severe. Therefore, it is difficult to provide an element having sufficient function with operational speed of TFT using an amorphous silicon film.
Hence, TFT utilizing a polycrystal silicon film (polysilicon film) has been spotlighted in place of an amorphous silicon film and development of TFT with a polycrystal silicon film as an active layer has been progressed with significant vigor. At present, product formation thereof has also been carried out partially.
Many presentations have already been carried out in respect of a structure of an inverted stagger type TFT utilizing a polycrystal silicon film as an active layer. For example, there have been reports of xe2x80x9cFabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method: H. Hayashi et. al., IEDM 95, pp.829-832, 1995xe2x80x9d, the disclosure of which is herein incorporated by reference, and so on.
According to the report, an explanation has been given of a typical example of an inverted stagger structure utilizing a polycrystal silicon film (FIG. 4), however, the inverted stagger structure of such a structure (so-called channel stop type) poses various problems.
First, a total of an active layer is extremely thin to about 50 nm and accordingly, impact ionization is caused at a junction between a channel forming region and a drain region and deteriorating phenomena of hot carrier injection and the like significantly emerge. Therefore, there causes a necessity of forming a large LDD region (Light Doped Drain Region).
Further, controllability of the LDD region for these is the most important problem. In an LDD region, control of a concentration of impurities and a length of the region is very delicate and particularly, control of length becomes problematic. At current state, a system for prescribing a length of an LDD region by a mask pattern is adopted, however, when miniaturization is promoted, slight patterning error causes a significant difference in properties of TFT.
A variation in sheet resistance of an LDD region caused by a variation in a film thickness of an active layer poses a serious problem. Further, a variation in a taper angle or the like of a gate electrode can be a factor causing a variation in the effect of an LDD region.
Further, a patterning step is needed to form an LDD region which gives rise to an increase in fabrication steps as it is and a deterioration in throughput. According to an inverted stagger structure described in the report mentioned above, it is anticipated that 6 sheets of masks at minimum (until formation of source and drain electrodes) are necessary.
As mentioned above, according to an inverted stagger structure of a channel stop type, LDD regions must be formed on both sides of a channel forming region and in a plane in the horizontal direction and it is very difficult to form a reproducible LDD region.
Further, the conventional AMLCD is provided with a structure in which a storage capacitance is installed to each pixel to compensate for leakage of electric charge held in a liquid crystal layer.
It is a problem of the present invention to provide a technology for fabricating a semiconductor device having high mass production performance and high reliability and reproducibility by very simple fabrication steps and to provide a constitution of a semiconductor device capable of fabricating without complicating steps and without particularly increasing a number of masks in fabricating a storage capacitance along with a bottom gate type TFT in a pixel matrix circuit and a method of fabricating thereof.
According to a first aspect of the present invention, there is provided a semiconductor device including a pixel matrix circuit comprising a plurality of gate wirings, a plurality of source wirings, a plurality of bottom gate type thin film transistors arranged to respective pixels and storage capacitances connected to pixel electrodes:
wherein a thin film semiconductor layer formed with a source region, a drain region and at least one channel forming region of each of the thin film transistors includes a crystal structure;
wherein each of the source region and the drain region includes a laminated layer structure comprising at least a first conductive layer, a second conductive layer having resistance higher than resistance of the first conductive layer and a first semiconductor layer having a conductive type the same as a conductive type of the channel forming region toward a gate insulating film;
wherein a concentration profile of an impurity for providing conductivities to the first and the second conductive layers is varied continuously from the first conductive layer to the second conductive layer; and
wherein the storage capacitance comprises a first electrode comprising a conductive film the same as the gate wiring, a dielectric body in contact with the first electrode and a second electrode comprising a second semiconductor layer in contact with the dielectric body and provided with a conductive type the same as the conductive type of the channel forming region.
Further, according to another aspect of the present invention, in the pixel matrix circuit having the above-described constitution, in place of using a semiconductor layer in the second electrode of the storage capacitance, the second electrode is formed by a conductive film common to a conductive film of the source wiring.
Further, according to another aspect of the present invention, in the pixel matrix circuit having the above-described constitution, the pixel electrode and the second electrode of the storage capacitance are formed by a conductive film common to a conductive film of the source wiring.
Further, according to another aspect of the present invention, in the pixel matrix circuit mentioned above, one electrode of the storage capacitance is formed by a conductive film common to a conductive film of the gate wiring, the pixel electrode includes a region in contact with a dielectric body of the storage capacitance and the pixel electrode is used for one electrode of the storage capacitance.
Further, in a thin film transistor arranged in a pixel matrix circuit according to the present invention, a thin film semiconductor layer in which source and drain regions and a channel forming region are formed, is provided with a grain boundary distribution particular to a film of molten crystals.
Further, according to another aspect of the present invention with regard to a method of fabricating a semiconductor device, there is provided a method of fabricating a semiconductor device comprising:
a step of forming the gate wirings and a first electrode of the storage capacitance over a substrate having an insulating surface;
a step of forming an insulating layer covering the gate wirings and the first electrode;
a step of forming an amorphous semiconductor film on the insulating layer;
a step of adding a catalyst element promoting crystallization to the amorphous semiconductor film and providing a semiconductor film having a crystal structure by a heating treatment;
a step of forming a conductive layer by adding an impurity selected from either of group 15 and group 13 or only group 15 to the semiconductor film having the crystal structure;
a step of gettering the catalyst element in the semiconductor film having the crystal structure to the conductive layer by a heating treatment;
a step of forming a first thin film semiconductor layer constituting a channel forming region of the thin film transistor and a second thin film semiconductor layer overlapping the first electrode via the insulating layer by patterning the semiconductor film having the crystal structure;
a step of forming the source wiring, a first conductive film covering at least regions for forming a source region and a drain region of the thin film transistor above the first thin film semiconductor layer and a second conductive film covering a surface of the second thin film semiconductor layer; and
a step of forming a channel forming region of the thin film transistor by etching the first thin film semiconductor layer with the first conductive film as a mask;
wherein a second electrode of the storage capacitance is formed in the second thin film semiconductor layer.
Further, according to another aspect of the present invention, in the pixel matrix circuit mentioned above, one electrode of the storage capacitance is formed by a conductive film common to a conductive film of the gate wiring, the pixel electrode includes a region in contact with a dielectric body of the storage capacitance and the pixel electrode is used for one electrode of the storage capacitance.
Further, in a thin film transistor arranged in a pixel matrix circuit according to the present invention, a thin film semiconductor layer in which source and drain regions and a channel forming region are formed, is provided with a grain boundary distribution particular to a film of molten crystals.
Although according to the fabrication method mentioned above, one electrode of the storage capacitance is formed in the semiconductor layer, according to other constitution with regard to a fabrication method of the present invention, a second electrode of the storage capacitance is formed with the source wiring and the source electrode and the drain electrode of the thin film transistor and a conductive film common to a conductive film of the source wiring is used as an electrode of the storage capacitance.
Further, according to other method, the pixel electrode is used for an electrode of the storage capacitance by forming the pixel electrode to be brought into contact with the pixel TFT and the dielectric body of the storage capacitance.